I have done some revamp of my SPI Master Controller core; in terms of hardware algorithm. The new code is a tad slower only by 8 SPI cycles more. This works just alike setup time; that is, the core needs 8 cycles to completely transfer the first byte to the 8 bit shift register.
Also, I have added mode and bit order selection for the core. It can work in both mode 0 and mode 3 that Spansion can support. Even though bit order is not useful for Spansion; this can be modified and used for any other device that supports both LSB first or MSB first modes of SPI transfer.
I have removed the top level decoding module which generates the lower level SPI commands for say a command like "Sector erase" which requires a "Write Enable" to be written first. I have left it for the terminal to do the job; pretty easier to do that way than waste resource on the FPGA. It currently uses 15% resources; the UART to SPI interface takes most of the resource and the controller core occupies only 2% of the Spansion 3A FPGA device.
I have uploaded the codes as well as the design document explaining the usage; the links of which can be found below.
'http://wikisend.com/download/899838/Spansion SPI Master Controller (With UART debug interface)_Rev1_0.doc'