Tuesday, July 28, 2009

UART to SPI interface finished

I have done some revamp of my SPI Master Controller core; in terms of hardware algorithm. The new code is a tad slower only by 8 SPI cycles more. This works just alike setup time; that is, the core needs 8 cycles to completely transfer the first byte to the 8 bit shift register.

Also, I have added mode and bit order selection for the core. It can work in both mode 0 and mode 3 that Spansion can support. Even though bit order is not useful for Spansion; this can be modified and used for any other device that supports both LSB first or MSB first modes of SPI transfer.

I have removed the top level decoding module which generates the lower level SPI commands for say a command like "Sector erase" which requires a "Write Enable" to be written first. I have left it for the terminal to do the job; pretty easier to do that way than waste resource on the FPGA. It currently uses 15% resources; the UART to SPI interface takes most of the resource and the controller core occupies only 2% of the Spansion 3A FPGA device.

I have uploaded the codes as well as the design document explaining the usage; the links of which can be found below.


'http://wikisend.com/download/899838/Spansion SPI Master Controller (With UART debug interface)_Rev1_0.doc'

Monday, April 20, 2009

Spansion Memory Controller

Though being a HW design engineer, programming has been an enticing experience for me for a very long time. Verilog HDL has been my favourite design tool thus far. I have worked previously on certain verilog modules like motor encoder, and other logic designs related to a motor controller board.

I have been thinking of developing a ogg vorbis audio decoder core (not a real time version that I am intending to work on at this moment; but simply a offline decoder) on my Avnet Spartan 3A evaluation board that I purchased a few months back. On an introductory note, this eval kit is really low cost (costs 39$) and has quite a lot of features to play with. I can say the evaluation board is simply great!

I decided to use the SPI flash memory from Spansion for storing the raw audio packets; due to the large memory storage. This board also comes with another parallel flash but only 32 Mega bits. I have been meaning to use this to store the FPGA configuration file; which will be quite large once I start working on the decoder core.

For the past few days, I was onto developing a SPI controller core in verilog for the Spansion memory (used in the board). By default configuration, it can be accessed via SPI controller module on the Cypress pSoC. But I decided to write my own core owing to 2 reasons; the SCLK on the pSOC seemed to be of the order of few KHz and the data communication mode between the FPGA and Cypress is either UART (obviously very slow) or SPI; which warrants a SPI Master Slave device on the FPGA if I intend to use SPI.

I have so far successfully developed the backend (or backbone) core which will generate the necessary signals. Today I wrote a small front end code to write 5 data bytes starting on a pre-destined address location (Hex 50000 till 50005) by touching capsense button "Push_A".

I, then, read back the values from the same 5 locations by touching capsense button "Push_B" and indicate it on the LED with a "1010" pattern if it is successful; otherwise the LEDs will be blinking.

Also, I did a bulk erase of the chip by touching capsense button "Push_C" which took around 1 min 8 seconds (safely can assume between 1 to 2 minutes which matches with the datasheet spec). I also read back the data from the same locations as before and the test failed as expected.

I am able to do most of the required operations that we want to do on a flash memory using the FPGA and the custom core. There are some open source cores available for SPI master. But I wanted to design my own one; this has given me enough confidence in working on more complex designs which I am intending to in the coming days.

I would be designing a proper front-end code; with an UART to SPI interface next. Inputs and feedbacks are most welcome!

Links for the source files for this initial revision: